The analog-to-digital converter (hereinafter referred to as an ADC as appropriate) is used in various fields. The required conversion speed and quantization bit rate of the ADC differ from system to system to which the ADC is applied. For example, in the ADC used for a communication purpose, as a signal band and a required SNR (Signal to Noise Ratio) differ depending on the communication scheme, the conversion speed and quantization bit rate required for the ADC also differ from communication scheme to communication scheme. Note that if the input range stays the same, the greater the quantization bit rate, the higher the conversion accuracy (SNR) of the ADC. That is, the conversion accuracy of the ADC is an index that depends on the size of the quantization bit width.
Here, FIG. 34 shows an example of a relationship between the conversion speed and conversion accuracy required for the ADC. FIG. 34 shows a relationship between signal bands of three modulation schemes, which are BPSK (Binary Phase-Shift Keying), QPSK (Quaternary Phase-Shift Keying), and 16PSK (16 Phase-Shift Keying), and SNRs that are required for the respective communication schemes. In BPSK, the required signal band is wide but the required SNR can be low. Therefore, an ADC with a high conversion speed and a low SNR is used for BPSK. Meanwhile, in 16PSK, the required signal band is narrow but the required SNR is high. Therefore, an ADC capable of achieving a high SNR is used for 16PSK even if a conversion speed thereof is low. Similarly, in QPSK, an ADC with a conversion speed between the conversion speeds required for BPSK and 16PSK and an SNR between the SNRs required for BPSK and 16PSK is used. As stated above, the performance required for the ADC differs from modulation scheme to modulation scheme. Thus, systems have heretofore been built using ADCs dedicated for the respective modulation schemes.
However, there has been a problem that the development cost and capital investment increase when different systems are used for different modulation schemes. In order to solve this problem, it is necessary to realize a highly flexible system that supports a plurality of requirement specifications. However, in order to realize a highly flexible system using a known ADC with a fixed conversion speed and conversion accuracy, an ADC with performance realizing a high conversion speed and high conversion accuracy at the same time is necessary. However, it is extremely difficult to realize such a high-speed and highly accurate ADC for a communication purpose in which the speed has been further accelerated in recent years. Even if such an ADC can be realized, the accuracy and the speed may be excessively or unnecessarily high for a certain modulation scheme, thereby leading to a problem of inefficiency and larger power consumption.
As a way to solve this problem, related art has already been suggested such as that disclosed in Patent Literature 1. The ADC of Patent Literature 1 uses a plurality of basic ADCs having the same performance. The ADC of Patent Literature 1 includes a time-interleaved configuration that operates the plurality of basic ADCs at different timings in the time-axis direction to thereby improve an apparent conversion speed. Moreover, the ADC of Patent Literature 1 includes an output average configuration that operates the plurality of basic ADCs at the same timing and averages outputs thereof to thereby reduce a random noise component other than quantization noise and improve the conversion accuracy. Further, the ADC of Patent Literature 1 arbitrarily combines the time-interleaved configuration and the output average configuration and flexibly switches the conversion speed and the conversion accuracy. However, the ADC of Patent Literature 1 uses averaging processing as a way to improve the conversion accuracy. Accordingly, even if the random noise component can be reduced, the quantization noise cannot be eliminated. It is therefore not possible to so improve the conversion accuracy that a quantization bit rate greater than or equal to the quantization bit rate of the basic ADC is achieved.
Meanwhile, as a similar approach, a related technique disclosed in Patent Literature 2 is a method for realizing an ADC having a quantization bit rate greater than or equal to the quantization bit rate of the basic ADC. In the ADC disclosed in Patent Literature 2, a plurality of basic ADCs are used to vary or shift a reference voltage that determines the quantization threshold of the ADC, thereby realizing an ADC having the quantization bit rate greater than or equal to the quantization bit rate of the basic ADCs. The configuration that realizes the ADC having the quantization bit rate greater than or equal to the quantization bit rate of the basic ADCs by varying or shifting the reference voltage that determines the quantization threshold of the ADC in a manner explained above shall be hereinafter referred to as an amplitude-interleaved configuration. However, the amplitude-interleaved configuration disclosed in Patent Literature 2 only improves the accuracy in the amplitude direction, while it is unable to achieve a conversion speed greater than or equal to the basic ADCs.